[97] | 1 | /*
|
---|
| 2 | ** Copyright 2012 by Kvaser AB, Mölndal, Sweden
|
---|
| 3 | ** http://www.kvaser.com
|
---|
| 4 | **
|
---|
| 5 | ** This software is dual licensed under the following two licenses:
|
---|
| 6 | ** BSD-new and GPLv2. You may use either one. See the included
|
---|
| 7 | ** COPYING file for details.
|
---|
| 8 | **
|
---|
| 9 | ** License: BSD-new
|
---|
| 10 | ** ===============================================================================
|
---|
| 11 | ** Redistribution and use in source and binary forms, with or without
|
---|
| 12 | ** modification, are permitted provided that the following conditions are met:
|
---|
| 13 | ** * Redistributions of source code must retain the above copyright
|
---|
| 14 | ** notice, this list of conditions and the following disclaimer.
|
---|
| 15 | ** * Redistributions in binary form must reproduce the above copyright
|
---|
| 16 | ** notice, this list of conditions and the following disclaimer in the
|
---|
| 17 | ** documentation and/or other materials provided with the distribution.
|
---|
| 18 | ** * Neither the name of the <organization> nor the
|
---|
| 19 | ** names of its contributors may be used to endorse or promote products
|
---|
| 20 | ** derived from this software without specific prior written permission.
|
---|
| 21 | **
|
---|
| 22 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
---|
| 23 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
---|
| 24 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
---|
| 25 | ** DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
---|
| 26 | ** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
---|
| 27 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
---|
| 28 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
---|
| 29 | ** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
---|
| 30 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
---|
| 31 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
---|
| 32 | **
|
---|
| 33 | **
|
---|
| 34 | ** License: GPLv2
|
---|
| 35 | ** ===============================================================================
|
---|
| 36 | ** This program is free software; you can redistribute it and/or
|
---|
| 37 | ** modify it under the terms of the GNU General Public License
|
---|
| 38 | ** as published by the Free Software Foundation; either version 2
|
---|
| 39 | ** of the License, or (at your option) any later version.
|
---|
| 40 | **
|
---|
| 41 | ** This program is distributed in the hope that it will be useful,
|
---|
| 42 | ** but WITHOUT ANY WARRANTY; without even the implied warranty of
|
---|
| 43 | ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
---|
| 44 | ** GNU General Public License for more details.
|
---|
| 45 | **
|
---|
| 46 | ** You should have received a copy of the GNU General Public License
|
---|
| 47 | ** along with this program; if not, write to the Free Software
|
---|
| 48 | ** Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
---|
| 49 | **
|
---|
| 50 | ** ---------------------------------------------------------------------------
|
---|
| 51 | **/
|
---|
| 52 |
|
---|
| 53 | #ifndef _TL16564_H_
|
---|
| 54 | #define _TL16564_H_
|
---|
| 55 |
|
---|
| 56 | // --- Addresses as seen from the subsystem (and some subsystem-only bit values)
|
---|
| 57 | #define TL_CTRL 0x110
|
---|
| 58 | #define TL_CTRL_COM1 0x00 /* We're COM1 when in address mode */
|
---|
| 59 | #define TL_CTRL_COM2 0x01 /* We're COM2 when in address mode */
|
---|
| 60 | #define TL_CTRL_COM3 0x02 /* We're COM3 when in address mode */
|
---|
| 61 | #define TL_CTRL_COM4 0x03 /* We're COM4 when in address mode */
|
---|
| 62 | #define TL_CTRL_CPUINT 0x04 /* Enable CPU interrupts via STSCHG# */
|
---|
| 63 | #define TL_CTRL_ADDRMODE 0x08 /* Enable Address Mode */
|
---|
| 64 | #define TL_CTRL_MODE_MASK 0x30
|
---|
| 65 | #define TL_CTRL_IO 0x10 /* I/O card */
|
---|
| 66 | #define TL_CTRL_MEM_BUSY 0x20 /* Memory card, BUSY */
|
---|
| 67 | #define TL_CTRL_MEM_READY 0x30 /* Memory card, READY */
|
---|
| 68 | #define TL_CTRL_RESET_IRQ 0x40 /* Reset subsystem IRQ signal */
|
---|
| 69 | #define TL_CTRL_BYPASS 0x80 /* Enable serial-bypass mode */
|
---|
| 70 |
|
---|
| 71 | #define TL_PGMCLK 0x120 // WO
|
---|
| 72 |
|
---|
| 73 | #define TL_MCR_B5 0x130 // WO - this is the auto-CTS bit
|
---|
| 74 | #define TL_DLL 0x130 // RO
|
---|
| 75 | #define TL_IER 0x131 // RO
|
---|
| 76 | #define TL_FCR 0x132 // RO
|
---|
| 77 | #define TL_LCR 0x133 // RO
|
---|
| 78 | #define TL_MCR 0x134 // RO
|
---|
| 79 | #define TL_LSR 0x135 // RO
|
---|
| 80 | #define TL_MSR 0x136 // RO
|
---|
| 81 | #define TL_DLM 0x137 // RO
|
---|
| 82 | #define TL_FIFO 0x140
|
---|
| 83 |
|
---|
| 84 |
|
---|
| 85 | // --- Addresses seen from the host (relative to the FIFO)
|
---|
| 86 | #define TLH_FIFO 0x00
|
---|
| 87 | #define TLH_IER 0x01
|
---|
| 88 | #define TLH_IIR 0x02 // RO
|
---|
| 89 | #define TLH_FCR 0x02 // WO
|
---|
| 90 | #define TLH_LCR 0x03
|
---|
| 91 | #define TLH_MCR 0x04
|
---|
| 92 | #define TLH_LSR 0x05
|
---|
| 93 | #define TLH_MSR 0x06
|
---|
| 94 | #define TLH_SCR 0x07
|
---|
| 95 | // When LCR.DLAB is set:
|
---|
| 96 | #define TLH_DLL 0x00
|
---|
| 97 | #define TLH_DLM 0x01
|
---|
| 98 |
|
---|
| 99 |
|
---|
| 100 |
|
---|
| 101 | // Various bit values in the control registers
|
---|
| 102 | /* Interrupt Enable Register, IER */
|
---|
| 103 | #define IER_ERBI 0x01
|
---|
| 104 | #define IER_ETBEI 0x02
|
---|
| 105 | #define IER_ELSI 0x04
|
---|
| 106 | #define IER_EDSSI 0x08
|
---|
| 107 |
|
---|
| 108 | /* Interrupt Identification Register, IIR */
|
---|
| 109 | #define IIR_NOINTPEND 0x01
|
---|
| 110 | #define IIR_ID1 0x02
|
---|
| 111 | #define IIR_ID2 0x04
|
---|
| 112 | #define IIR_ID3 0x08
|
---|
| 113 | #define IIR_FIFO_IS_ENA1 0x40
|
---|
| 114 | #define IIR_FIFO_IS_ENA2 0x80
|
---|
| 115 |
|
---|
| 116 | // The values for different interrupt reasons
|
---|
| 117 | #define IIR_INTID_MASK 0x06
|
---|
| 118 | #define INT_RCV_LINE_STATUS 0x06 // 110
|
---|
| 119 | #define INT_RCV_DATA 0x04 // .100
|
---|
| 120 | #define INT_TX_HOLD_REG_EMPTY 0x02 // 010
|
---|
| 121 | #define INT_MODEM_STATUS 0x00 // 000
|
---|
| 122 | #define INT_CHAR_TIMEOUT 0x0c // 1100
|
---|
| 123 |
|
---|
| 124 | /* FIFO Control Register, FCR */
|
---|
| 125 | #define FCR_FIFO_ENABLE 0x01
|
---|
| 126 | #define FCR_RXFIFO_RESET 0x02
|
---|
| 127 | #define FCR_TXFIFO_RESET 0x04
|
---|
| 128 | #define FCR_DMAMODE 0x08
|
---|
| 129 | #define FCR_FDEPTH64 0x20 // Note: "reserved" in 16C550C
|
---|
| 130 | #define FCR_AUTO_RTS 0x10 // Note: "reserved" in 16C550C
|
---|
| 131 |
|
---|
| 132 | /* Line Control Register, LCR */
|
---|
| 133 | #define LCR_WLS0 0x01
|
---|
| 134 | #define LCR_WLS1 0x02
|
---|
| 135 | #define LCR_STOPBITS 0x04
|
---|
| 136 | #define LCR_PARITY_ENABLE 0x08
|
---|
| 137 | #define LCR_EVEN_PARITY 0x10
|
---|
| 138 | #define LCR_STICK_PARITY 0x20
|
---|
| 139 | #define LCR_BREAK 0x40
|
---|
| 140 | #define LCR_DLAB 0x80
|
---|
| 141 |
|
---|
| 142 | /* Modem Control Register, MCR */
|
---|
| 143 | #define MCR_DTR 0x01
|
---|
| 144 | #define MCR_RTS 0x02
|
---|
| 145 | #define MCR_OUT1 0x04
|
---|
| 146 | #define MCR_OUT2 0x08
|
---|
| 147 | #define MCR_LOOP 0x10
|
---|
| 148 | /* This bit has another meaning in the 564:
|
---|
| 149 | #define MCR_AFE 0x20
|
---|
| 150 | */
|
---|
| 151 | /* This definition isn't meaningful in the 564:
|
---|
| 152 | #define MCR_AUTOFLOW 0x22 // Both AFE and RTS
|
---|
| 153 | */
|
---|
| 154 | #define MCR_RESERVED1 0x20
|
---|
| 155 |
|
---|
| 156 |
|
---|
| 157 | /* Line Status Register, LSR */
|
---|
| 158 | #define LSR_DATA_READY 0x01
|
---|
| 159 | #define LSR_OVERRUN 0x02
|
---|
| 160 | #define LSR_PARITY_ERR 0x04
|
---|
| 161 | #define LSR_FRAMING_ERR 0x08
|
---|
| 162 | #define LSR_BREAK_INT 0x10
|
---|
| 163 | #define LSR_THRE 0x20
|
---|
| 164 | #define LSR_TEMT 0x40
|
---|
| 165 | #define LSR_RCVERR 0x80
|
---|
| 166 |
|
---|
| 167 | /* Modem Status Register, MSR */
|
---|
| 168 | #define MSR_DELTA_CTS 0x01
|
---|
| 169 | #define MSR_DELTA_DSR 0x02
|
---|
| 170 | #define MSR_TERI 0x04
|
---|
| 171 | #define MSR_DELTA_DCD 0x08
|
---|
| 172 | #define MSR_CTS 0x10
|
---|
| 173 | #define MSR_DSR 0x20
|
---|
| 174 | #define MSR_RI 0x40
|
---|
| 175 | #define MSR_DCD 0x80
|
---|
| 176 |
|
---|
| 177 | #endif // _TL16564_H_
|
---|